Size 25 and 40 Single-turn and Geared DigiSolvers

ELECTRICAL
Input Power:
    Voltage: 5 VDC +/- 5%, or 8-30 VDC
    Current: 0.55 A, Single-turn; 0.75 A, Multi-turn
Power-on Settling Time:
    For 130 ms after power is turned ON, the encoder
    output is frozen as follows:
    T & N: all zeros
    P & C: all ones
    After 130 ms, the DigiSolver reads the TRUE position.
POSITION OUTPUT:
Output Format and Number of Words/Counts:
a) Single-turn and Geared Single-turn Units:
    Gray Code (G): 256, 512, 1024, 4096, and 8192
    Binary (B): 1024, 4096, and 8192
    BCD (D): 360, 100, and 3600
    (Custom Counts available consult factory)
    Analog (A): 4-20 mA (sinking or sourcing) or 0-10 VDC
    output, 0.1% Repeatability, 1% Accuracy of full scale.
    (Consult factory for higher accuracy models)
    Built-in Gear Ratios: 2:1, 3:1, 4:1, 8:1, 12:1, 16:1, 20:1,
    24:1, 32:1, 36:1, 40:1, 48:1, 60:1, 64:1, 80:1, 100:1
b) Multi-turn Units:
    18-bit Binary over 64 turns , 12-bit per revolution, 6-bits
    for 64 turns. 15-bit BCD or Gray Code over 32 turns,
    10-bits per revolution, 5-bits for 32 turns, Built-in gear
    train of 64:1 or 32:1
OUTPUT DRIVERS:
T: Tristate (Multiplexing): TTL (74LS 645), high logic TRUE
    Logic True: 2V @ 15 mA, 20 mA leakage when tristated
    Logic False: 0.35 V @ 24 mA, 0.4 mA leakage when
    tristated MUX input: Low active, TTL level
P: Source Transistor: Vmax = 30 V, high Logic TRUE
    (Sprague UDN-2981A)

    Logic TRUE: Transistor ON, 1.7 V drop @ 100 Ma
    Logic FALSE: Transistor OFF, 0.2 mA leak. @ 50 V.
    On ES the P-type outputs are short-circuit-proof and are
    rated 20 mA @ 50 VDC
N: Sink Transistor: Vmax = 30V, low Logic TRUE
    (Sprague ULN-2803A)
    Logic TRUE: Transistor ON, 1.1 V drop @ 100 mA
    Logic FALSE: Transistor OFF, 0.1 mA leak. @ 50 V.
C: Sink Transistor: Vmax = 30 V, high Logic TRUE
    (Sprague ULN-2803A)
    Logic TRUE: Transistor OFF, 0.1 mA leak. @ 50 V
    Logic FALSE: Transistor ON, 1.1 V drop @ 100 mA.
OUTPUT TIMING:
P: PLC Synchronization Option: Encoder position data
    is latched 50 μs to 3 ms (factory set at 3 ms,
    field-adjustable) after either transition edge of data
    transfer command from PLC (Nonretriggerable during
    timing period).
O: Transparent/Microfreeze Option: Encoder position
    data is continuously updated at full speed. The data
    is frozen (Microfreeze) for 100 +/- 10% μs within
    10 μs of either transition edge of data transfer
    command. Data transfer command is not required if     Microfreeze is not needed.
    Data Transfer Command:
    TTL compatible, 2200 internal pull-up to 5 V, high
    Logic TRUE, edge-triggered.
    High level: 3.5 to 30 VDC
    Low level: 0 to 1 VDC
    Pulse width: Minimum 10 μs
OPTIONAL OUTPUTS:
Analog Tach Output:
    100 RPM/Vot for 0 to +10 VDC (0 Volt = 0 RPM)
    or 100 RPM/1.6 mA for 4-20 mA (4 mA = 0 RPM).
Direction Output: TTL, HIGH = CCW, LOW = CW
Revolution Count (Marker Pulse):
    Negative pulse, TTL, pulse